Digbijay Mahanta posted an Question
December 15, 2019 • 05:56 am 15 points
  • IIT JAM
  • Physics (PH)

SECTION-(C) NUMERICAL ANSVVER TYPE UUESTIOND IWAUJ Find out the minimum number of NAND gates required to implement A+ AB+ABC assian (/A RL AC)

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    Somnath

    Two numbers of NAND gate required to implement the output.For details see the attachment.

    upload_1576387367479.jpg
    upload_1576387499051.jpg
  • comment-profile-img>
    Somnath

    Two numbers of NAND gate required to implement the output.For details see the attachment.

    upload_1576387367479.jpg
  • comment-profile-img>
    Somnath best-answer

    Two numbers of NAND gate required to implement the output.For details see the attachment.

    upload_1576387367479.jpg
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